(1) Field of the Invention
This invention relates to a dynamic random access memory (DRAM) device and more particularly, to a method for fabricating storage capacitors on DRAM cells with fin-shaped and vertical sidewall electrodes, and thereby providing increased capacitance.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) circuits are used extensively in the electronics industry for storing information as binary data. The DRAM circuit formed on chips diced from semiconductor substrates consists of an array of memory cells, and peripheral circuits for randomly accessing the memory cells. The individual memory cells, comprising of a single field effect transistor (FET) and a charge storage capacitor, have been significantly reduced in size, and the array of cells on the chip have dramatically increased. For example, by the year 1998 the number of memory cells on the DRAM chip are expected to increase four fold reaching an expected 256 million cells (256 Megabits chip). The dramatic increase in the number of memory cells is a result of improved semiconductor processing technologies, such as high resolution photolithography and directional plasma etch to name a few. The device minimum feature size on the chip are now less than a half micrometer (um) and are expected to be a quarter micrometer by the year 1998.
In order to maintain a reasonable DRAM chip size while increasing the number of storage cells on the chip it is necessary to decrease the horizontal dimensions of the memory cell and the capacitor that is formed in each cell. However, the accompanying reduction in capacitance makes it difficult to maintain an acceptable signal-to-noise level and each capacitor also requires more frequent refresh cycles to retain the charge that dissipates with time. Therefore, there is a strong need in the industry to maintain or increase the capacitance in each memory cell while reducing the area that the capacitor occupies on the DRAM cell.
A trench storage capacitor formed in the substrate adjacent to the FET, and a stacked storage capacitor formed over the FET on the substrate are two common approaches for making the memory cell storage capacitors. Of the two approaches the stacked capacitor has received considerable interest, in recent years, because of the variety of ways that the capacitor electrodes can be formed in the vertical (third) dimension over the FET and within the cell area to increase the capacitance while maintaining or reducing the cell area.
A number of methods have been reported for making stacked capacitors with increased capacitance. For example, H. T. Lui et al in U.S. Pat. No. 5,396,456 H. describe a method for making a stacked capacitor having a tub shape capacitor for increasing the capacitance. In U.S. Pat. No. 4,742,018 by S. Kimura et al, a capacitor is described having a second conducting extension formed on the bottom electrode of the capacitor to increase the capacitance. Another approach is described in U.S. Pat. No. 5,053,351 by P. Fazan et al, in which the bottom electrode is E-shaped to increase capacitance and is called a E-cell capacitor DRAM cell. Still another DRAM cell is described in U.S. Pat. No. 5,021,357 by M. Taguchi et al, in which a multilayer of dissimilar materials are selectively etched to form the capacitor bottom electrode with increased surface area.
Although the above methods provide a means for increasing the capacitance on stacked capacitors for DRAM, there is still a need in the semiconductor industry to provide methods that further increase capacitance while providing a cost effective manufacturing process.